Industrial Quality Prediction System through Data Mining Algorithm
Volume-3 | Issue-2
Comparative Analysis an Early Fault Diagnosis Approaches in Rotating Machinery by Convolution Neural Network
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Nakagami-m Fading Detection with Eigen Value Spectrum Algorithms
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Abstractive Summarization System
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Design of Adaptive Estimator for Nonlinear control system in Noisy Domain
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Automated Nanopackaging using Cellulose Fibers Composition with Feasibility in SEM Environment
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Comparative Analysis of Temperature Measurement Methods based on Degree of Agreement
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Transistor Sizing using Hybrid Reinforcement Learning and Graph Convolution Neural Network Algorithm
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A Review on Meshing Techniques in Biomedicine
Volume-3 | Issue-4
EL DAPP - An Electricity Meter Tracking Decentralized Application
Volume-2 | Issue-1
SMART STREET SYSTEM WITH IOT BASED STREET LIGHT OPERATION AND PARKING APPLICATION
Volume-1 | Issue-1
ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET
Volume-1 | Issue-1
Abstractive Summarization System
Volume-3 | Issue-4
A Review on Meshing Techniques in Biomedicine
Volume-3 | Issue-4
MIMO BASED HIGH SPEED OPTICAL FIBER COMMUNICATION SYSTEM
Volume-1 | Issue-2
Industrial Quality Prediction System through Data Mining Algorithm
Volume-3 | Issue-2
Comparative Analysis of Temperature Measurement Methods based on Degree of Agreement
Volume-3 | Issue-3
Transistor Sizing using Hybrid Reinforcement Learning and Graph Convolution Neural Network Algorithm
Volume-3 | Issue-3
VIRTUAL REALITY SIMULATION AS THERAPY FOR POSTTRAUMATIC STRESS DISORDER (PTSD)
Volume-1 | Issue-1
Comparative Analysis an Early Fault Diagnosis Approaches in Rotating Machinery by Convolution Neural Network
Volume-3 | Issue-2
Volume - 2 | Issue - 4 | december 2020
Published
19 January, 2021
In this paper, an encoder and decoder system is proposed using Bose-Chaudhuri-Hocquenghem (BCH) double-error-correcting and triple-error detecting (DEC-TED) with emerging memories of low power and high decoding efficiency. An adaptive error correction technique and an invalid transition inhibition technique is enforced to the decoder. This is to improve the decoding efficiency and reduce the power consumption and delay. The adaptive error correction gives high decoding efficiency and invalid transition technique reduce the power consumption issue in conventional BCH decoders. The DEC-TED BCH decoder combines these two techniques by using a specific Error Correcting Code Clock and Flip Flops. This technique provides an error correcting encoder and decoder solution for low power and high-performance application using emerging memories. The design simulated in Xilinx FPGA using ISE Design Suite 14.5.
KeywordsBose-Chaudhuri-Hocquenghem (BCH) code Adaptive error correction Invalid transition inhibition emerging memories
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