KARTHIGAIKUMAR, P. Transistor Sizing using Hybrid Reinforcement Learning and Graph Convolution Neural Network Algorithm. Journal of Electronics and Informatics, [S. l.], v. 3, n. 3, p. 194–208, 2021. DOI: 10.36548/jei.2021.3.004. Disponível em: https://irojournals.com/iroei/article/view/470. Acesso em: 21 mar. 2026.