Journal of Electronics and Informatics
type: channel
publisher: Inventive Research Organization
language: en
publication name: Journal of Electronics and Informatics
issn: 2582-3825
items: Design of Fuzzy Logic based Soft Starter for Induction Motor
items: Neural Network based Soft Starting Technique for Squirrel Cage Induction Motor
items: Simulation and Implementation of 7-Level and 27-Level Cascaded H-Bridge Multilevel Inverter for Reduced THD Under R and RL Loads
items: Resource-Efficient FPGA Implementation of a Self-Attention Core for Edge AI
items: Pressure Sensing on Natural Leaf Scaffolds
items: Next Generation IoT Framework for Smart LPG Cylinder Monitoring, Safety Detection and Autonomous Refill Booking
items: AI-Enabled Smart Bus System for Modern Urban Mobility
items: Construction Site Worker’s Safety Detection System
items: Aqua Sense: Smart IoT System for Water Usage and Quality Monitoring
items: Intelligent Accident Prevention and Alert System Using Sensors and Machine Learning
items: AI-Powered Real-Time Diagnosis of Neuromuscular Disorders Using EMG and Gait Analysis
items: High-Data-Retention 6T SRAM with Dual Sleep-Transistor Power-Gating and Duty-Cycle Aware Energy Analysis for Low-Power IoT Application
items: Power Electronic and Embedded System Co-Design for Scalable Smart Energy Network Optimization
items: Quantum Semiconductor Devices: Current Progress and Future Trends
items: Study on Thin-Film Transistor and Circuit Design Using Artificial Intelligence
items: Analysis of Learning-Based Methods for Intelligent Edge Computing
items: An Area Efficient Lifting Wavelet for ECG R-peak Detection Applications
items: EdgeSNN-RT: Low-Overhead Spiking Simulation on Embedded GPUs for On-Device Intelligence
items: Bioinformatics-Driven Automation in Hydroponics: Nutrient Management System and Growth Prediction Model
items: Optimized Double Tail Comparator based ADC for High Speed and Low Power Applications
items: Enhancement of Underwater Images using Texture Distribution Mapping Method
items: Performance Analysis of High-Speed Parallel Prefix Adders for Arithmetic Applications
items: FPGA Based 32-Bit Hybrid Ripple Ling Carry Adder
items: Development of a Hybrid Energy Storage System using Batteries and Supercapacitors
items: Power Flow Analysis for the Steel Industry
items: Enhanced Fault Detection for FPGA-based Elliptic Curve Cryptography
items: Secured E-Banking using Multi-Identity based Fully Homomorphic Encryption
items: Fiber Optic Network Innovations to Bypass the Red Sea Route
items: A Comparative Study on Hashing Algorithms for Data Integrity and Efficiency
items: Underground Cable Fault Analysis by Distance Calculation and Location Detection using Microcontroller and GPS

Design of Fuzzy Logic based Soft Starter for Induction Motor
type: item
description: Induction motors are extensively used across all industrial applications due to the robustness, comparatively less cost and very low maintenance. Nevertheless, at startup, this kind of motors pull a largely high current about several times larger than the rated value harming both. Several starting methods have been employed to minimize the in-rush current and overcome this problem. Previously, conventional starting methods: direct-on-line (DOL), star-delta and autotransformer starters have been utilized since they generally provide minimal relative control of starting performance. This paper presents a soft starting technique for three-phase squirrel cage induction motor using fuzzy logic controller (FLC) based approach. The proposed solution uses a power electronic AC voltage regulator to slowly decrease stator voltage at start up, which reduces start current and torque fluctuations. A fuzzy logic controller uses from linguistic rules and membership function in determining the control action, based on the inputs (current error and its derivative). Simulation and analysis validate the proposed method. The results clarify a significant drop in inrush current and attaining a soft torque which improves the overall performance and service life of the motor. The proposed system offers a more stable start and effective operation of motor cores over conventional starting method
subject: Articles
  topic: section
subject: Fuzzy Logic Control (FLC)
  topic: keywords
subject: Soft Starting
  topic: keywords
subject: Squirrel Cage Induction Motor
  topic: keywords
subject: Starting Current
  topic: keywords
subject: Torque Ripple
  topic: keywords
subject: Motor Control
  topic: keywords
creator: Mohamed Faizal A.A.
creator: Sathya V.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-06-10
publication date: 2026-06-10
starting page: 200
ending page: 216
doi: 10.36548/jei.2026.3.001

Neural Network based Soft Starting Technique for Squirrel Cage Induction Motor
type: item
description: The soft start of squirrel cage induction motors is highly imperative in order to avoid any excessive currents, torque pulses, and mechanical stresses. As a matter of fact, traditional Direct on Line (DOL) techniques of motor starting involve heavy current transients and torque pulses that tend to shorten the life of the motors and destabilize system performance. In this regard, this paper presents a soft starting scheme for a three-phase squirrel cage induction motor using an artificial neural network (ANN) based on a thyristor-controlled AC voltage controller. The proposed feed-forward multilayer perceptron (MLP) ANN model incorporates various motor operating parameters including motor current, speed, electromagnetic torque, and loading condition to provide optimal firing angles of the thyristors. The induction motor is represented in dq-coordinates while the MLP ANN is trained by means of backpropagation algorithm with the performance index being Mean Squared Error (MSE). From the MATLAB simulations, the results indicate that the proposed ANN model can significantly decrease the starting current from 90A to 30A and starting torque from 125N-m to 40N-m compared to the traditional DOL scheme.
subject: Articles
  topic: section
subject: Artificial Neural Network (ANN)
  topic: keywords
subject: Soft Starting
  topic: keywords
subject: Squirrel Cage Induction Motor
  topic: keywords
subject: Starting Current
  topic: keywords
subject: Torque Ripple
  topic: keywords
subject: Motor Control
  topic: keywords
creator: Mohamed Faizal A.A.
creator: Muthulakshmi M.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-05-20
publication date: 2026-05-20
starting page: 188
ending page: 199
doi: 10.36548/jei.2026.2.007

Simulation and Implementation of 7-Level and 27-Level Cascaded H-Bridge Multilevel Inverter for Reduced THD Under R and RL Loads
type: item
description: In this paper, 7 and 27 levels of cascaded H-bridge Multilevel Inverter systems are modeled and implemented, where different sub-MLI devices are interconnected in series for producing a large amount of power. The main objective in this work is to achieve a higher output voltage with less power switches. Renewable energy sources are mostly in DC form and hence should be converted properly in DC-AC to be connected to the grid. This is achieved by inverters, and multilevel inverters are preferred as they are able to produce high-quality AC. The CHB-MLI is one of the most common types due to its modularity, simplicity and high quality output, to name a few. The more the number of DC voltage levels, the better the output voltage waveform approaches a pure sinusoidal waveform, and thus lower the harmonic distortion. This research aims to achieve a close to sinusoidal output waveform and to analyse system performance in terms of comparing the Total Harmonic Distortion (THD) of different levels of CHB-MLIs. 7-level inverter is implemented in hardware and the 27-level inverter is designed and analysed using MATLAB/Simulink and hardware for both resistive (R) and resistive-inductive (RL) loads.
subject: Articles
  topic: section
subject: MLI - Multilevel Inverter
  topic: keywords
subject: CHB - Cascaded H-Bridge
  topic: keywords
subject: THD - Total Harmonic Distortion
  topic: keywords
subject: SPWM - Sinusoidal Pulse Width Modulation
  topic: keywords
subject: MATLAB/Simulink
  topic: keywords
subject: Renewable Energy
  topic: keywords
subject: R Load
  topic: keywords
subject: RL Load
  topic: keywords
creator: Amuthanantham K.
creator: Elakkiya S.
creator: Chunchurambabu
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-05-19
publication date: 2026-05-19
starting page: 171
ending page: 187
doi: 10.36548/jei.2026.2.006

Resource-Efficient FPGA Implementation of a Self-Attention Core for Edge AI
type: item
description: The Modern AI relies on transformer-based architectures, they require considerable resource requirements along with substantial memory requirements for implementation in resource-limited deployments due to their inherent computational complexity. The use of Field Programmable Gate Arrays (FPGAs) to create an efficient hardware accelerator for self-attention within transformers will allow for efficient use of hardware resources while enabling the use of transformers as part of an edge AI system. This research describes the implementation of such a design using the Xilinx Artix-7 FPGA platform with the Nexys DDR development board and demonstrates the capability of self-attention within an FPGA-based hardware accelerator to produce results in real time through a pipelined multiply-accumulate (MAC) architecture and finite state machine (FSM) based control structures. In addition, the implementation of this hardware accelerator was able to achieve functional accuracy when compared to the Python Golden Model. The hardware accelerator produced low levels of both hardware utilization and power consumption while at the same time providing a efficient computational performance. The architecture provides a unique solution for balancing performance, resource utilization and energy efficiency. FPGA-based domain-specific accelerators have demonstrated their ability to bridge the computational gap presented by transformer self-attention mechanisms and would be an appropriate method for implementing real-time inference of edge AI systems.
subject: Articles
  topic: section
subject: FPGA Accelerator
  topic: keywords
subject: Self-Attention
  topic: keywords
subject: Transformer Models
  topic: keywords
subject: Edge Computing
  topic: keywords
subject: Fixed-Point Design
  topic: keywords
subject: Pipelined MAC
  topic: keywords
subject: BRAM-Based Architecture
  topic: keywords
subject: Low-Latency Processing
  topic: keywords
subject: Energy-Efficient Computing
  topic: keywords
creator: Janaki Rani M.
creator: Mohana Divya S.
creator: Kavya D.
creator: Maniyammai B.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-05-02
publication date: 2026-05-02
starting page: 156
ending page: 170
doi: 10.36548/jei.2026.2.005

Pressure Sensing on Natural Leaf Scaffolds
type: item
description: Flexible and sustainable pressure sensors have received considerable focus recently for use in wearable electronics, biometric monitoring, and human-machine interfaces. This study introduces a cheap, flexible pressure sensor using a composite material made of graphene and metal oxide deposited on a natural leaf scaffold. The hierarchical structure provided by the leaf scaffold improves the mechanical flexibility and sensitivity of the sensor. On the other hand, the composite layer enhances electrical conductivity and the piezoresistive effect. The sensor works based on the change in resistance when subjected to external pressure and uses a microcontroller to acquire and process data in real-time. A coin is used to calibrate the system to produce consistent pressure from 0.11 to 2.20 kPa. Finally, linear regression analysis is performed to obtain a correlation equation between the output voltage and pressure. Using this correlation, the output voltage can be predicted accurately without further calibration of the sensor.
subject: Articles
  topic: section
subject: Flexible Sensors
  topic: keywords
subject: Leaf Scaffolds
  topic: keywords
subject: Graphene Nanocomposite
  topic: keywords
subject: Piezoresistive Sensing
  topic: keywords
subject: Sustainable Electronics
  topic: keywords
creator: Kavitha G.
creator: Krishnaraj S.
creator: Mohanraj D.
creator: Mohanraj K.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-05-02
publication date: 2026-05-02
starting page: 146
ending page: 155
doi: 10.36548/jei.2026.2.004

Next Generation IoT Framework for Smart LPG Cylinder Monitoring, Safety Detection and Autonomous Refill Booking
type: item
description: The proposed Next-Generation IoT Framework for Smart LPG Cylinder Monitoring, Safety Detection, and Autonomous Refill Booking is an intelligent solution aimed at ensuring increased safety, energy savings, and convenience in LPG use. This system is comprised of sensors such as load sensor, gas leak detector, pressure and temperature sensor coupled with a low power microcontroller and wireless communication module like NB-IoT or LoRaWAN. Load sensor helps in determining the quantity of LPG left in the cylinder based on its current weight. The sensors can detect any leakage in the gas, changes in pressure and temperature, or any movement and raise instant alarm along with alerting remotely in real time. Cloud backend will carry out further analysis and trigger refill booking automatically with the help of gas services provider through secure API integration.
subject: Articles
  topic: section
subject: Internet of Things (IoT)
  topic: keywords
subject: Smart LPG Monitoring
  topic: keywords
subject: Gas Leakage Detection
  topic: keywords
subject: Real-Time Monitoring
  topic: keywords
subject: Safety Alert System
  topic: keywords
creator: Akhil A.
creator: Geetha Reddy G.
creator: Sukumar G.
creator: Lakshminarayanan N.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-05-02
publication date: 2026-05-02
starting page: 133
ending page: 145
doi: 10.36548/jei.2026.2.003

AI-Enabled Smart Bus System for Modern Urban Mobility
type: item
description: The rapid urbanization and increasing demand for efficient public transportation systems necessitate the adoption of intelligent and automated solutions to overcome the limitations of conventional transport management. Traditional bus systems, which rely on manual ticketing and human supervision, often suffer from issues such as revenue leakage, lack of transparency, inefficient passenger monitoring, and security vulnerabilities. This research presents an AI-Enabled Smart Bus System for Modern Urban Mobility that integrates Internet of Things (IoT), cloud computing, and machine learning techniques to enhance operational efficiency, safety, and user experience. The proposed system utilizes an ESP32 microcontroller as the central processing unit, interfaced with RFID-based smart card technology for contactless ticketing, IR sensors for accurate passenger counting, GPS module for real-time vehicle tracking, and ESP32-CAM for surveillance and unauthorized access detection. Passenger data is continuously collected and transmitted to a cloud-based platform for real-time monitoring and storage. Machine learning algorithms implemented in Python are employed for anomaly detection, fraud identification, and passenger demand prediction, enabling data-driven decision-making and optimized route management. Furthermore, an auxiliary Arduino Uno module is incorporated to handle seat selection and stop request operations, thereby improving system responsiveness and reducing computational load. The proposed framework ensures high accuracy, reduced human intervention, enhanced security, and efficient resource utilization. The results demonstrate that the system is scalable, cost-effective, and well-suited for deployment in smart city environments, contributing to sustainable and intelligent urban transportation systems.
subject: Articles
  topic: section
subject: AI-Enabled Transport System
  topic: keywords
subject: Internet of Things (IoT)
  topic: keywords
subject: RFID Smart Card Ticketing
  topic: keywords
subject: Machine Learning
  topic: keywords
subject: GPS-Based Tracking
  topic: keywords
subject: Cloud Computing
  topic: keywords
subject: Passenger Monitoring and Safety
  topic: keywords
creator: Vimala T.
creator: Raghul A.
creator: Sakthivel S.
creator: Sai Krishna M.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-04-29
publication date: 2026-04-29
starting page: 120
ending page: 132
doi: 10.36548/jei.2026.2.002

Construction Site Worker’s Safety Detection System
type: item
description: The construction sites are one of the most dangerous workplaces, due to the presence of machinery, tall buildings, and unsafe practices at work. One of the main factors leading to accidents is the incorrect use of personal protective equipment (PPE) like safety helmets, safety glasses, safety footwear, and reflective jackets by employees. Besides, there are cases of undetected health problems that lead to injuries. Traditional approaches to safety monitoring involve human inspection and periodical examination of workers, which are time-consuming, prone to errors, and do not work effectively on large-scale construction sites. The goal of this research is the development of an intelligent worker safety detection algorithm for the smart construction site that would incorporate machine vision–based detection of PPEs and Internet of Things (IoT) technologies for health monitoring. The algorithm detects safety helmet and reflective jacket using machine vision based on deep learning algorithms, while body temperature is detected using a DS18B20 sensor interfaced with an ESP32 microcontroller. A decision-making mechanism confirms safety of the conditions and sends a warning message in case any violation or abnormal situation is observed.
subject: Articles
  topic: section
subject: Construction Site Safety
  topic: keywords
subject: Personal Protective Equipment
  topic: keywords
subject: Deep Learning
  topic: keywords
subject: IoT
  topic: keywords
subject: ESP32
  topic: keywords
subject: Temperature Monitoring
  topic: keywords
creator: Abishek N.
creator: Vasanth P.G.
creator: Ramya G.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-04-29
publication date: 2026-04-29
starting page: 109
ending page: 119
doi: 10.36548/jei.2026.2.001

Aqua Sense: Smart IoT System for Water Usage and Quality Monitoring
type: item
description: Water scarcity and water quality degradation are becoming significant global issues due to rapid urbanization and improper water management practices. This paper proposes a smart IoT-based system named Aqua Sense, which can be used for real-time monitoring of water consumption and water quality in water tanks, cities, and commercial areas. In the proposed system, water flow, water level, pH, TDS, and turbidity sensors are connected to an ESP32 microcontroller for real-time monitoring of water parameters. A threshold-based approach and an alert counter are used for efficient water parameter monitoring. Moreover, motor control is also included in the proposed system for efficient water management, which can prevent water overflow and motor dry running. All the operations of the proposed system are stored in a cloud database, which can be accessed remotely using a mobile or web-based application. The experimental results of the proposed system show efficient water parameter monitoring, water savings, and increased awareness of water consumption. The proposed system can be used as a cost-effective, efficient, and reliable solution for water management systems.
subject: Articles
  topic: section
subject: IoT-based Water Monitoring
  topic: keywords
subject: Smart Water Management
  topic: keywords
subject: ESP32 Microcontroller
  topic: keywords
subject: Water Quality Analysis
  topic: keywords
subject: Real-Time Data Visualization
  topic: keywords
creator: Akash P.
creator: Chittesh S.
creator: Naveenkumar M.
creator: Vikram G.
creator: Sujitha K.
creator: Kanmani G.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-03-26
publication date: 2026-03-26
starting page: 93
ending page: 108
doi: 10.36548/jei.2026.1.006

Intelligent Accident Prevention and Alert System Using Sensors and Machine Learning
type: item
description: Road accidents are one of the primary causes of death around the globe, and these can be avoided if timely actions are taken by the driver of the vehicle. This paper proposes a system known as the Intelligent Accident Prevention and Alert System, which makes use of various sensors and machine learning algorithms to predict potential hazards on the road in real time. This system utilizes data from various sensors such as accelerometers, gyroscopes, GPS, proximity sensors, and driver sensors. This data is fed into a feature extraction module, where a random forest algorithm is utilized to classify the level of risk of an accident occurring. Based on this, an alert signal is sent to the driver, enabling them to take timely action. A feedback mechanism has been included in the system to ensure dynamic risk assessment. The performance of the proposed system is evaluated through a scenario-based simulated dataset, and the results show an accuracy of 93.5%, thereby proving the efficiency and reliability of the proposed system in detecting hazardous driving conditions. The proposed system also provides timely alerts, thereby enhancing the efficiency and effectiveness of accident prevention. The results prove that the proposed system offers an efficient and effective solution for accident prevention in real-world applications.
subject: Articles
  topic: section
subject: Intelligent Accident Prevention System (IAPAS)
  topic: keywords
subject: Machine Learning
  topic: keywords
subject: Sensor Fusion
  topic: keywords
subject: Risk Prediction
  topic: keywords
subject: Driver Alert System
  topic: keywords
subject: Intelligent Transportation Systems
  topic: keywords
creator: Kavitha K.
creator: Jayanth Arivazhagan
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-03-25
publication date: 2026-03-25
starting page: 81
ending page: 92
doi: 10.36548/jei.2026.1.005

AI-Powered Real-Time Diagnosis of Neuromuscular Disorders Using EMG and Gait Analysis
type: item
description: The proposed project aims to develop an online diagnostic system that can optimally integrate gait analysis and electromyography (EMG) signal processing to diagnose neuromuscular and neurodegenerative diseases in patients. The proposed system can utilize computer vision to detect abnormal gait patterns in patients. The abnormal gait patterns can include abnormal stride patterns, shuffling gait, freezing gait, and balance problems. The proposed system can utilize an EMG sensor to detect muscle activity in patients. The EMG sensor can be connected to an ESP8266 module to send muscle activity data wirelessly to a computer system using a WebSocket server. An online dashboard can be created to visualize muscle activity and gait patterns in patients. The proposed system can be an affordable and mobile AI-based system that can aid in early disease diagnosis in patients and provide better accessibility to healthcare services.
subject: Articles
  topic: section
subject: Electromyography (EMG)
  topic: keywords
subject: Gait Analysis
  topic: keywords
subject: Neuromuscular Disorders
  topic: keywords
subject: OpenCV
  topic: keywords
subject: WebSocket server
  topic: keywords
subject: Streamlit
  topic: keywords
subject: Artificial Intelligence (AI)
  topic: keywords
creator: Gowtham M.
creator: Anbumuthu P.
creator: Harikrishnan M.
creator: Muthukumar T.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-03-23
publication date: 2026-03-23
starting page: 68
ending page: 80
doi: 10.36548/jei.2026.1.004

High-Data-Retention 6T SRAM with Dual Sleep-Transistor Power-Gating and Duty-Cycle Aware Energy Analysis for Low-Power IoT Application
type: item
description: Static Random Access Memory (SRAM) is the main contributor to standby power dissipation in duty-cycled Internet of Things (IoT) systems. The paper presents a 6 transistor SRAM cell that has low leakage and dual sleep transistor-based power gating. The memory cell is mode aware and supports different modes of operation. The header PMOS and footer NMOS sleep transistors have been used to minimize leakage and retain stored information during extended periods of sleep. The proposed memory architecture is validated through 45 nm CMOS models and simulations in LT spice. The memory is able to achieve picoampere levels of supply current in deep sleep mode. A duty cycle aware analysis of energy dissipation is also presented. The analysis shows that the proposed memory is an effective solution for ultra-low-power memory in IoT systems.
subject: Articles
  topic: section
subject: Low-Power SRAM
  topic: keywords
subject: Dual Sleep Transistor
  topic: keywords
subject: Power Gating
  topic: keywords
subject: Data Retention
  topic: keywords
subject: Deep Sleep Mode
  topic: keywords
subject: IoT Applications
  topic: keywords
subject: Leakage Reduction
  topic: keywords
creator: Varshitha K.
creator: Boya Sri Vyshnavi Valmiki
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-03-20
publication date: 2026-03-20
starting page: 52
ending page: 67
doi: 10.36548/jei.2026.1.003

Power Electronic and Embedded System Co-Design for Scalable Smart Energy Network Optimization
type: item
description: The existing electrical infrastructure changed into digital, distributed and renewable-based methods develop smart energy networks required for constant interaction of power devices with advanced control systems. The usage of electric cars, distributed energy resources and energy storage increased to allow two-way transfer of power, varied load response provide challenges to coordination, efficiency conversion and scalability operation. This study explains technological system for combining power electronic converters and embedded system architecture for scalable smart energy network optimization. The advanced converter architecture, temperature management, hardware optimization algorithms and integrated sensor interface provide effective operations of distributed energy systems. The embedded control platforms, communication infrastructure units and supervisory energy management techniques are the examples of multilayer architectural model. This research shows integrated hardware-software designs improve system ability for effective power regulation and scalability of distributed energy resource implementations. The detailed design data develops robust and smart power electronic infrastructures for next-generation smart energy networks.
subject: Articles
  topic: section
subject: Smart Energy Networks
  topic: keywords
subject: Power Electronic Converters
  topic: keywords
subject: Circuit–System Co-Design
  topic: keywords
subject: Embedded Energy Management
  topic: keywords
subject: Digital Twin Integration
  topic: keywords
subject: Hardware-Aware Optimization
  topic: keywords
subject: Distributed Smart Grids
  topic: keywords
creator: Bindhu V.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-03-17
publication date: 2026-03-17
starting page: 27
ending page: 51
doi: 10.36548/jei.2026.1.002

Quantum Semiconductor Devices: Current Progress and Future Trends
type: item
description: Modern electronics are frequently used in quantum semiconductor devices. The devices are extremely small and their behavior cannot be described by traditional theories. The impacts include quantum confinement and tunneling. Several new quantum devices have been proposed in the past, including an examination of their theory and design. Additionally, new modeling methods are being developed. Atomic-scale production has been shown to be constantly increasing. This effort addresses several issues at the same time. As a result, the device's dependability remains a challenge, produce variations have an impact on performance, cooling and thermal management are not easy to perform. This study reviews recent achievements in quantum semiconductor devices. It discusses device characteristics, modeling and production methods. It also identifies current disadvantages and unsolved challenges that minimize future effort are addressed in detail.
subject: Articles
  topic: section
subject: Quantum Semiconductor Devices
  topic: keywords
subject: Quantum Confinement
  topic: keywords
subject: Device Modeling
  topic: keywords
subject: Atomic-scale Production
  topic: keywords
subject: Quantum Transport
  topic: keywords
subject: Future Trends
  topic: keywords
creator: Rahimunnisa K.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-02-21
publication date: 2026-02-21
starting page: 1
ending page: 26
doi: 10.36548/jei.2026.1.001

Study on Thin-Film Transistor and Circuit Design Using Artificial Intelligence
type: item
description: This paper reviews the detailed inspection of the current situation of thin-film transistors (TFT) and circuit design using AI, its widespread applications, and the future changes that are about to take place in this field. In liquid crystal display (LCD) systems, thin-film transistors have bridged the gap between the technologies used in this application and have been employed in a wide variety of areas, such as flexible electronics, biological sensing, and integrated IoT platforms. The focus of the paper is on the areas where TFT is heading rather than those it has already traversed. A close look at the sectors reveals that high-resolution displays, where TFT is integrated, result from some vibrant circuits made on flexible substrates, which would not be possible without TFT. Artificial intelligence can be applied to predict and enhance manufacturing efficiency and to estimate costs more accurately. Integrating TFT thin-film transistors with AI integrated circuits in future electronic devices will represent a significant advancement in the field. The AI built-in circuit type augmented by thin-film transistors would unlock visionary progress in entrenched high-tech areas and provide a unique and innovative gateway for businesses and researchers.
subject: Articles
  topic: section
subject: Thin-Film Transistor (TFT)
  topic: keywords
subject: Artificial Intelligence
  topic: keywords
subject: Liquid Crystal Displays (LCDs)
  topic: keywords
subject: Integrated Circuits (IC’s)
  topic: keywords
creator: Manoharan S.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-01-10
publication date: 2026-01-10
starting page: 298
ending page: 315
doi: 10.36548/jei.2025.4.004

Analysis of Learning-Based Methods for Intelligent Edge Computing
type: item
description: Edge Computing is recognized as an important computing paradigm that helps in the processing of data as well as the making of decisions near the user, hence reducing the need to rely on cloud infrastructure. Edge Computing is of high importance in fields that are sensitive to latency, such as smart vehicles, IoT services, health monitoring, UAVs, and smart cities. Edge Computing environments face various issues, such as limited computational power, network variability, mobility, and the need to process high volumes of diverse tasks. These issues in edge computing are difficult to handle using traditional methods of optimization. Deep Reinforcement Learning (DRL) algorithms are significantly used in edge computing systems as an intelligent decision-making tool that can optimize decisions through interactions with the edge computing system. This review paper presents a comprehensive analysis of recent studies and representative research that apply DRL techniques to edge computing systems. The reviewed papers cover various applications such as vehicular edge computing, IoT-based multi-access edge computing, UAV-assisted edge computing, collaboration between fog and cloud computing, and blockchain and federated learning-based edge computing systems. The discussion on DRL applications encompasses task offloading, resource management, workload management, caching, and mobility management. A comparative analysis discusses the most used DRL algorithms and their applications along with performance improvements. Additionally, this literature review highlights some of the main drawbacks of DRL, such as training complexity, scalability, privacy, and deployment, and identifies areas that require improvement to create safe and efficient DRL-based edge computing solutions.
subject: Articles
  topic: section
subject: Edge Computing
  topic: keywords
subject: Deep Reinforcement Learning
  topic: keywords
subject: Task Offloading
  topic: keywords
subject: Resource Allocation
  topic: keywords
subject: Internet of Things (IoT)
  topic: keywords
subject: Vehicular Edge Computing
  topic: keywords
creator: Nay Myo Sandar
creator: Thinzar Aung Win
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-01-07
publication date: 2026-01-07
starting page: 281
ending page: 297
doi: 10.36548/jei.2025.4.003

An Area Efficient Lifting Wavelet for ECG R-peak Detection Applications
type: item
description: Noise removal is a vital pre-processing step in wearable ECG devices for accurate arrhythmia detection. This paper proposes a hardware-efficient, multiplier-less FPGA architecture for ECG denoising using a lifting-based wavelet transform. A universal thresholding function with soft thresholding enhances signal quality, while a modified lifting-based DWT eliminates multipliers and simplifies computation. An optimized median calculation and thresholding method remove the need for comparators in VLSI design. ECG data from the MIT-BIH databases validate the approach, achieving an SNR improvement of 7.4 dB and an MSE of 0.0206. FPGA implementation on the Nexys 4 DDR board demonstrates low hardware usage and a high operating frequency of 166 MHz, outperforming existing designs.
subject: Articles
  topic: section
subject: FPGA
  topic: keywords
subject: Biomedical ECG Wearables
  topic: keywords
subject: Noise Reduction in ECG Signals
  topic: keywords
subject: Lifting-based DWT
  topic: keywords
subject: Adaptive Soft Thresholding
  topic: keywords
creator: Ravi Teja C.
creator: Dharani M.
creator: Kavitha Y.
creator: Bhoomika V.
creator: Imran S.
rights: Copyright (c) 2026 Journal of Electronics and Informatics
date: 2026-01-06
publication date: 2026-01-06
starting page: 267
ending page: 280
doi: 10.36548/jei.2025.4.002

EdgeSNN-RT: Low-Overhead Spiking Simulation on Embedded GPUs for On-Device Intelligence
type: item
description: EdgeSNN-RT proposes a Python-managed, GPU-accelerated spiking neural network simulation method optimized for edge platforms, integrating their definition, execution, and, critically, low-cost host-device synchronization. A dense spike bitfield logging tool groups spikes on the device, obviating the need for one-timestep communication, yielding up to 10x cost savings for logging spikes. Experiments conducted for full-scale cortical microcircuit simulation and long-term conditioning tasks with large time horizons range across variant models of diversified, consumer-class, and larger-scale, heterogeneous GPUs, from the low-power, as-specified, 15W Jetson Xavier NX, to measure the latency, kernel execution time, and interpretative overheads of their execution in the real-time regime specifically for the purposes of the challenge. The system supports real-time or faster simulation execution for today’s leading-class GPUs, and, for shared-memory architectures of embedded platforms, preserves their leading performance with direct, low-level control, NumPy direct views to the managed buffers, and an events-based representation of plasticity within a convenient API. On-device inference and learning of spiking neural networks for real-world tasks will become feasible for networks of the described architecture based on this work, mapping telemetry, memory representation, and scheduling approaches to fit within limitations imposed by embedded platforms, supplanting today's restricted assumptions about direct, one-step execution communication and/or awaiting improvements in physical implementation technology for general programmed computation targets from desktop workstations back toward rudimentary, network-edge platforms in an industry led by programmability for applied innovation.
subject: Articles
  topic: section
subject: Spiking Neural Networks
  topic: keywords
subject: GPU Acceleration
  topic: keywords
subject: Edge Computing
  topic: keywords
subject: Embedded Systems
  topic: keywords
subject: Python
  topic: keywords
subject: CUDA
  topic: keywords
creator: Girish Chanda
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-12-19
publication date: 2025-12-19
starting page: 247
ending page: 266
doi: 10.36548/jei.2025.4.001

Bioinformatics-Driven Automation in Hydroponics: Nutrient Management System and Growth Prediction Model
type: item
description: Effective nutrient management is needed for hydroponic farming. Herein, a bioinformatics-driven automation system that incorporates growth prediction models, automated dosing of nutrients, and real-time analysis of sensor data for optimal plant growth is introduced. For control and monitoring in real-time, a microcontroller is coupled with calibrated TDS, pH, and EC sensors. TDS differentials are used to predict nutrient uptake, and a pH- and EC-based regression model is employed to predict plant height. The technique was validated using a range of plants like tomatoes, lettuce, and beans. Without relying on IoT infrastructure, the outcome is higher nutrient efficiency and accurate height prediction, offering a scalable and cost-effective alternative to existing systems.
subject: Articles
  topic: section
subject: Hydroponics
  topic: keywords
subject: Automation
  topic: keywords
subject: Nutrient Management
  topic: keywords
subject: Data Synthesis
  topic: keywords
subject: Regression Model
  topic: keywords
creator: Latha Mercy E.
creator: Anandhan R.
creator: Arun M.
creator: Karan S.
creator: Prasath D.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-08-12
publication date: 2025-08-12
starting page: 233
ending page: 246
doi: 10.36548/jei.2025.3.004

Optimized Double Tail Comparator based ADC for High Speed and Low Power Applications
type: item
description: Dynamic regenerative comparators are being used to increase speed and power efficiency in response to the need for ultra-low-power, area-efficient, and high-speed analog-to-digital converters. This study suggests using two transistors to create a low power double-tail comparator for the Flash Analog-to-Digital Converter. Designing a comparator and thermometer code to binary code converter at low supply voltage and low power dissipation is a challenging task in the creation of a low power Flash ADC. The primary goal is to construct comparators in order to achieve a high-speed Flash ADC. We should design each comparator to have a lower total power consumption because the comparators in Flash ADC are power-hungry components. Here, a low-power dynamic comparator is being designed. Next, we used a 2:1 MUX based on pass transistor logic to construct an encoder block. We have constructed a 5-bit Flash ADC using these components. To lower the Flash ADC's power consumption, a comparator and encoder are implemented utilizing dynamic CMOS circuitry. The Tanner EDA back-end tool is used to run the simulation.
subject: Articles
  topic: section
subject: Tanner EDA
  topic: keywords
subject: Comparator
  topic: keywords
subject: Flash ADC
  topic: keywords
subject: Encoder
  topic: keywords
subject: Multiplexer
  topic: keywords
subject: and Dynamic Double Tail
  topic: keywords
creator: Dadasikandar Kanekal
creator: Sowjanya Baisani
creator: Suhas Jayaramappa Gari
creator: Neelima Mangala
creator: Jagan Gulipagi
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-08-05
publication date: 2025-08-05
starting page: 220
ending page: 232
doi: 10.36548/jei.2025.3.003

Enhancement of Underwater Images using Texture Distribution Mapping Method
type: item
description: In either situation, underwater vision is affected by low light, diffraction, and color aberrations that lead to image distortion. To prevent this, we implemented a Texture Distribution Mapping Approach for undersea image improvement using MATLAB. Under this framework, we will enhance texture distribution, contrast, and visibility in general by controlling the most relevant properties of texture in the underwater environment. The TDM process is incremental: it involves pre-processing to eliminate noise and color distortion, followed by enhancement using another method for texture improvement. By enhancing texture mapping onto the image, we achieve a balance of visibility in high-texture regions, resulting in low-texture regions and better clarity and coloring. The method was compared against real underwater image data sets and tested for performance using quality measures like UCIQE (Underwater Color Image Quality Evaluation) and UIQM (Underwater Image Quality Measure). Experimental results and MATLAB implementation of the proposed algorithm exhibited stunning improvements in image quality and luminosity enhancements in texture compared to baseline methods, especially in challenging water conditions.
subject: Articles
  topic: section
subject: UCIQE
  topic: keywords
subject: UIQM
  topic: keywords
subject: TDM
  topic: keywords
subject: MSE
  topic: keywords
subject: PSNR
  topic: keywords
creator: Preetam Mandal
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-08-01
publication date: 2025-08-01
starting page: 206
ending page: 219
doi: 10.36548/jei.2025.3.002

Performance Analysis of High-Speed Parallel Prefix Adders for Arithmetic Applications
type: item
description: Research on affordable adder architectures has been spurred by the need for high-performance arithmetic in digital and embedded signal processors. Carry propagation affects speed, area, and power consumption by limiting two-operand addition, a fundamental operation in these systems. Because of their versatility in modifying particular performance metrics, Parallel Prefix Adders (PPAs) represent a viable substitute. The performance of various PPAs, including Kogge-Stone, Sparse Kogge-Stone, Spanning Tree, Brent-Kung, Han-Carlson, and Ladner-Fischer, on a Virtex-7 FPGA with Xilinx Vivado 2022.2 is investigated in this paper. The findings imply that each PPA design performs well in its own way and that no single design can offer the best balance of power, latency, and area. By taking performance parameter trade-offs into account, the research helps designers choose the best PPA for their design needs.
subject: Articles
  topic: section
subject: Digital Signal Processors (DSP). Parallel Prefix Adders (PPAs)
  topic: keywords
subject: Xilinx Vivado. Virtex FPGA
  topic: keywords
creator: Banumathi J.
creator: Karthy G.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-07-29
publication date: 2025-07-29
starting page: 191
ending page: 205
doi: 10.36548/jei.2025.3.001

FPGA Based 32-Bit Hybrid Ripple Ling Carry Adder
type: item
description: The 32-bit Hybrid Ripple Ling carry adder uses a Ling-based parallel prefix adder for the upper 16 bits and a ripple-carry adder (RCA) for the lower 16 bits to optimize performance, power, and area efficiency for VLSI designs. While the Ling adder speeds up carry propagation for larger bits, the RCA minimizes area and power for smaller bit-widths. This hybrid structure offers high-speed, low-power operation while saving 12% power, 30%–40% area, and a worst-case delay of 0.182 ns in a 28 nm process. The adder employs a Ling-based parallel prefix topology for the higher-order bits. A re-expression of the carry-lookahead technique is used to construct ling adders, which reduce the complexity of the carry-propagation process and allow for a higher speed carry calculation. The Ling adder's parallel prefix character suggests that multiple bits' carry signals are computed in parallel, significantly reducing the total delay. For the higher-order bits, where the carry chain length would normally be the dominant critical path, this speedup is especially important. The hybrid adder increases the global speed of the addition operation by reducing the critical path by using a Ling adder for the upper bits. The Xilinx Zynq-7000 SoC is used for the implementation.
subject: Articles
  topic: section
subject: Ripple-Ling hybrid carry adder
  topic: keywords
subject: Ripple-carry adder (RCA)
  topic: keywords
subject: Carry-lookahead adder
  topic: keywords
subject: Ling-based parallel prefix adder
  topic: keywords
subject: Carry propagation
  topic: keywords
subject: Critical Path
  topic: keywords
creator: Neenu Joseph
creator: Ashker Assis
creator: Arjun Bibin
creator: Aromal A.
creator: Thanzeel A R.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-07-01
publication date: 2025-07-01
starting page: 177
ending page: 190
doi: 10.36548/jei.2025.2.008

Development of a Hybrid Energy Storage System using Batteries and Supercapacitors
type: item
description: The development of hybrid energy storage systems (HESS), which combine batteries and supercapacitors, has accelerated due to the need for dependable and efficient energy storage. Batteries have a high energy density, but their lifespan and charge/discharge rates are limited. Supercapacitors, on the other hand, have a lower energy capacity but offer long life and quick charging. This paper presents a low-cost, practical HESS for real-time energy delivery that uses inverter output control, supercapacitor buffering, and voltage regulation based on the LM317. Improved efficiency (up to 96%), thermal stability, and voltage regulation under variable load conditions are confirmed by experimental results. Applications for the system include solar-integrated energy units, UPS systems, and EVs.
subject: Articles
  topic: section
subject: Hybrid Energy Storage Systems
  topic: keywords
subject: Batteries
  topic: keywords
subject: Supercapacitors
  topic: keywords
subject: Energy Management
  topic: keywords
subject: Power Density
  topic: keywords
subject: Electric Vehicles
  topic: keywords
subject: Renewable Energy
  topic: keywords
creator: Preetha K.
creator: Santhosh M.
creator: Keerthana S.
creator: Sriharaiharan V.
creator: Elankumar G.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-07-01
publication date: 2025-07-01
starting page: 167
ending page: 176
doi: 10.36548/jei.2025.2.007

Power Flow Analysis for the Steel Industry
type: item
description: Significant equipment like electric arc furnaces (EAFs) and ladle refining furnaces (LRFs) are among the highly dynamic and nonlinear electrical loads found in steel production facilities like Surana Industry. Reactive power imbalance, harmonic distortion, and voltage instability are just a few of the significant power quality issues caused by these complex loads. Because of this, accurate modeling and thorough analysis of these complex power systems are essential to ensuring operational dependability and maintaining power quality. The current literature tends to emphasize mostly steady-state conditions that are frequently not verified empirically with respect to actual operating data, despite the fact that the Electrical Transient Analyzer Program (ETAP) is a common tool used for load flow analysis in industry applications. With an emphasis on accurately simulating the real system behavior under various operating regimes, this paper provides a thorough power flow analysis of the Surana Steel Industry using ETAP. Two 100 MVA, 220/110 kV transformers step down the 110 kV supply that powers the plant, which is drawn from the Chikkasagur substation. The primary loads—a 35-ton rolling mill, a 4 MW EAF, and an LRF are supplemented with a captive power generation system and a harmonic filter to improve power quality and reliability. Under five different operating conditions with different load levels and generator configurations, key performance metrics such as voltage regulation, reactive power flow, harmonic suppression, and generator dynamic response are thoroughly assessed. The power system of the Surana Steel Industry is accurately simulated by the analytical method employed here. Even though a real-time comparison with SCADA data was not attempted, the ETAP model was painstakingly built with detailed equipment specs, typical operating conditions, and performance patterns actually observed at the facility. Accurate simulation of industrial environments, including the…
subject: Articles
  topic: section
subject: Surana Industry
  topic: keywords
subject: Steel Industry
  topic: keywords
subject: High Voltage
  topic: keywords
subject: Transformers
  topic: keywords
subject: Load
  topic: keywords
subject: Rolling Mill
  topic: keywords
subject: Electric Arc Furnace
  topic: keywords
subject: Ladle Refining Furnace
  topic: keywords
subject: Harmonic Filter
  topic: keywords
subject: Generation
  topic: keywords
subject: Efficiency
  topic: keywords
subject: Scenarios
  topic: keywords
subject: ETAP
  topic: keywords
creator: Harsha Varthini P.B.
creator: Yasoda K.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-06-20
publication date: 2025-06-20
starting page: 143
ending page: 166
doi: 10.36548/jei.2025.2.006

Enhanced Fault Detection for FPGA-based Elliptic Curve Cryptography
type: item
description: For secure communications in particular, elliptic curve cryptography relies heavily on Elliptic Curve Scalar Multiplication (ECSM). The window approach is perfect for FPGA-based solutions since it increases ECSM efficiency. Verifying the accuracy of calculations made by hardware or software is essential to spotting possible mistakes. In this study, we introduce new defect detection strategies for scalar multiplication using the window method, which has not been studied in detail. Our strategy entails creating intricate algorithms and implementations to successfully minimize both transient and permanent faults. We validate our method's correctness by simulating a failure model, proving its dependability and broad error coverage in our assessments.
subject: Articles
  topic: section
subject: Elliptic Curve Scalar Multiplication (ECSM)
  topic: keywords
subject: Elliptic Curve cryptography (ECC)
  topic: keywords
subject: Communication Window method
  topic: keywords
subject: FPGA
  topic: keywords
subject: Error detection
  topic: keywords
creator: Kiruthika G.
creator: Udhaya M.
creator: Swetha A.
creator: Priyanka B.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-06-13
publication date: 2025-06-13
starting page: 133
ending page: 142
doi: 10.36548/jei.2025.2.005

Secured E-Banking using Multi-Identity based Fully Homomorphic Encryption
type: item
description: In today's digital landscape, ensuring the security of e-banking platforms is crucial for preventing unauthorized access and safeguarding sensitive financial information. This project employs Fully Homomorphic Encryption (FHE), a significant advancement in cryptography that enables the processing of encrypted data without the need for decryption, thereby preserving privacy throughout the transaction. A pivotal aspect of the system is its encrypted authentication mechanism, which protects login credentials, including usernames and passwords. Additionally, the platform introduces a multi-identity authentication model, allowing users to engage with the system under various secure roles. By integrating FHE with a multi-identity framework, the system provides robust protection against cyber threats.
subject: Articles
  topic: section
subject: Fully Homomorphic Encryption
  topic: keywords
subject: Cyber Security
  topic: keywords
subject: Data privacy
  topic: keywords
subject: Access Control
  topic: keywords
subject: Multi-identity
  topic: keywords
subject: Encrypted processing
  topic: keywords
subject: Digital Banking
  topic: keywords
creator: Sundaramoorthy K.
creator: Lokanya G.
creator: Ashlin Prajaa P. J.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-05-27
publication date: 2025-05-27
starting page: 122
ending page: 132
doi: 10.36548/jei.2025.2.004

Fiber Optic Network Innovations to Bypass the Red Sea Route
type: item
description: This ambitious project seeks to establish a robust, high-speed fiber optic network that will connect Europe with South Asia through a terrestrial route spanning Saudi Arabia, Iraq, Turkey, Bulgaria, Hungary, and Austria. The project presents a strategic alternative to traditional maritime internet cables, which often traverse underwater routes from Europe to South Asia. By relying on a land-based network, this initiative aims to mitigate some of the risks associated with undersea cables, such as disruptions caused by natural disasters, shipping accidents, or geopolitical tensions in maritime zones. One of the key components of this project is infrastructure development. This involves laying extensive fiber optic cables, building data centers, and ensuring that the network is both secure and scalable. Unlike the challenges faced by undersea networks, land-based infrastructure allows for easier maintenance, potential expansions, and faster upgrades to meet future demands for higher data speeds and increased bandwidth. Technology integration plays a crucial role as well. Advanced networking technologies like 5G, edge computing, and cloud services can be integrated into this fiber optic network, enabling the efficient handling of vast amounts of data and enhancing overall performance. The deployment of state-of-the-art technologies will also help in reducing latency, improving user experience, and fostering innovation in the region.
subject: Articles
  topic: section
subject: Monitoring
  topic: keywords
subject: integrated development environment
  topic: keywords
subject: Internet of Things
  topic: keywords
subject: Fiber optic network
  topic: keywords
subject: service level agreement
  topic: keywords
creator: Raj E.
creator: Dhanalakshmi K. M.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-05-23
publication date: 2025-05-23
starting page: 112
ending page: 121
doi: 10.36548/jei.2025.2.003

A Comparative Study on Hashing Algorithms for Data Integrity and Efficiency
type: item
description: In recent years, the widespread availability of image editing tools has led to the proliferation of phony and manipulated photos on the Internet and social media. Various techniques have been developed to detect image forgery and identify altered or fabricated regions, with a growing emphasis on deep learning (DL) methods. This study explores recent advances in DL-based forgery detection algorithms, focusing on the detection of copy-move and splicing attacks two of the most common image tampering techniques. Additionally, the challenges posed by DeepFake-generated content, which often mimics splicing manipulation, are discussed. The study also compares hashing algorithms (SHA-256, CRC32, Random Projection Hashing, and Count-Min Sketch) for use in data integrity, similarity searches, and frequency estimation. Finally, recommendations for selecting suitable algorithms and hybrid approaches are provided to enhance image authentication and large-scale data analysis.
subject: Articles
  topic: section
subject: Image forgery detection
  topic: keywords
subject: deep learning
  topic: keywords
subject: copy-move attack
  topic: keywords
subject: splicing attack
  topic: keywords
subject: Deep Fake detection
  topic: keywords
subject: data integrity
  topic: keywords
subject: hashing algorithms
  topic: keywords
subject: SHA-256
  topic: keywords
subject: CRC32
  topic: keywords
subject: Random Projection Hashing
  topic: keywords
subject: Count-Min Sketch
  topic: keywords
subject: similarity detection
  topic: keywords
subject: streaming data analytics
  topic: keywords
subject: probabilistic data structures
  topic: keywords
creator: Atshaya R.
creator: Bhavatharni J.
creator: Darshana S.B.
creator: Ismankhan Y.M.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-05-20
publication date: 2025-05-20
starting page: 95
ending page: 111
doi: 10.36548/jei.2025.2.002

Underground Cable Fault Analysis by Distance Calculation and Location Detection using Microcontroller and GPS
type: item
description: In today’s power distribution systems, underground cables are preferred for their safety and tidy appearance. However, detecting faults in these cables can be slow, costly, and technically challenging. This study introduces a smart fault detection and location system that uses the PIC16F887 microcontroller as its core. It sends a low DC voltage through the cable and uses voltage and current sensors to monitor for irregularities. Based on the changes in readings, the system estimates the fault distance using Ohm’s Law. To pinpoint the exact location, a GPS module is included. The fault details are shown on an LCD and also transmitted through GSM for SMS alerts. Additionally, the ESP8266 Wi-Fi module allows the data to be shared online for remote monitoring. This solution provides faster and more accurate fault detection, reducing repair time and improving the reliability of underground cable systems.
subject: Articles
  topic: section
subject: PIC16F887
  topic: keywords
subject: ESP8266
  topic: keywords
subject: GSM
  topic: keywords
subject: Voltage Sensor
  topic: keywords
subject: Current Sensor
  topic: keywords
subject: GPS
  topic: keywords
creator: Aswanth S.
creator: Shanmugapriya V.
creator: Praveen Kumar S.
creator: Padmanaban T.
creator: Sowmya A K.
creator: Manjupriya R.
rights: Copyright (c) 2025 Journal of Electronics and Informatics
date: 2025-05-09
publication date: 2025-05-09
starting page: 80
ending page: 94
doi: 10.36548/jei.2025.2.001