Energy-Efficient Neuromorphic Architectures Enabled by Resistive Memory - Sharma, Joshika; Akashe, Shyam (Journal of Trends in Computer Science and Smart Technology, 2025)
Their excellent performance and compatibility with CMOS technology, while the OXRAM (Oxide-based CMOS Resistive Random Access Memory) technique used in CMOS transistors presents challenges in terms of device unpredictability and scalability, also offers potential advantages such as higher endurance, lower power consumption, and quicker reading and writing operation speeds when compared to traditional Flash memory. The inability of conventional SRAMs to store data after powering off limits their use in battery-operated mobile devices and other applications where non-volatility related to zero leakage currents is required. In the article, a new OXRAM-based Non-Volatile SRAM (NVSRAM) device is presented. It is suggested to compare the performance of SRAM with NVSRAM at the memory and cell levels. Learning is crucial for the brain's ability to adapt to changing conditions. A synaptic connection table in an external memory at a local routing node is used to learn a rule in the address domain for neuromorphic architecture. A number of parameters are compared, including design complexity, leakage current values (SRAM cells are 3.4µA, 7.4nA) and (NVSRAM-based OXRAM are 2.7 µA, 5.9nA) at 180nm and 90nm, and energy saving or power usage values (SRAM cells cell are 5.5 µA, 10.5nA) and (NVSRAM based OXRAM are 4.9 µA, 9.8nA) at 180nm and 90nm. The circuits that are being described can be realized using far-above ground voltage CMOS Cadence tools at 180 nm and 90 nm.
Keywords: Static Random CMOS Access Memories (SRAMs); Non-Volatile CMOS SRAM (NVCSRAM); OXRAM; Power Dissipation; Technology