Abstract
This research presents an efficient development of a multi-rate Finite Impulse Response (FIR) filter utilizing Distributed Arithmetic (DA) for digital signal processing (DSP) applications. The motivation behind this work lies in the increasing demand for high-performance filters in various multimedia and communication systems, where low power consumption and area-efficient designs are critical. The proposed FIR filter utilizes DA to minimize the resource requirements typically associated with conventional filter implementations while achieving comparable or improved performance metrics. A Look-Up Table (LUT) based approach is employed to compute filter outputs, allowing for rapid and efficient processing of input samples. Simulation results demonstrate that the multi-rate FIR filter significantly minimizes the computational complexity and enhances speed, Optimizing it for real-time performance in embedded systems. The findings emphasize the significance of integrating Distributed Arithmetic into FIR filter designs., paving the way for more advanced signal-processing solutions in VLSI architectures. This proposed design is implemented using Vivado version 2023 in Zynq UltraScale + MPSoCs family.
References
- Ali, Zulfiqar, Sania Syed, Syed Tahir Hussain Shah, Wesam Khalil, and Muhammad Ayaz. "Multirate FIR Filter Using Radix Sort Booth Algorithm In Xilinx System Generator." In 2022 International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC), Pakistan, IEEE, 2022. 1-6.
- D. Vaithiyanathan, K. Mariammal and B. P. James, "Performance Analysis of Multirate Filter Structures for Signal Processing Applications," 2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON), Bangalore, India, 2023, 1-7,
- V.Lesnikov, T. Naumovich and A. Chastikov, "Matrix Multiplication Using Distributed Arithmetic," 2021 23rd International Conference on Digital Signal Processing and its Applications (DSPA), Moscow, Russian Federation, 2021, 1-5.
- T. Soni, A. Kumar and M. K. Panda, "Modified Efficient Parallel Distributed Arithmetic based FIR Filter Architecture for ASIC and FPGA," 2023 10th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2023, 860-865,
- L. Singh, Geetanjali and R. Mehra, "FPGA based Optimized Decimator using Distributed Arithmetic Algorithm for Wireless Applications," 2021 6th International Conference for Convergence in Technology (I2CT), Maharashtra, India, 2021, 1-6.
- R. Vinay, T. S. V. S. Vijayakumar, L. M. Saini and B. Singh, "Power efficient FIR filter Architecture using Distributed Arithmetic Algorithm," 2020 First IEEE International Conference on Measurement, Instrumentation, Control and Automation (ICMICA), Kurukshetra, India, 2020, 1-4.
- M. Bharathi and Y. J. M. Shirur, "VLSI Synthesis of Multiply and Accumulate Structures Using Distributed Arithmetic," 2023 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE), Bengaluru, India, 2023, 166-169.
- A. H. A. Bayoumi, S. A. Ibrahim and H. A. H. Fahmy, "Fast Parallel Multiple Access Distributed Arithmetic (FPMA-DA) Reconfigurable FIR Filter," 2023 International Conference on Microelectronics (ICM), Abu Dhabi, United Arab Emirates, 2023, 1-6.
- H. Jiang, L. Liu, P. P. Jonker, D. G. Elliott, F. Lombardi and J. Han, "A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, Jan. 2019, 313-326.
- N. S. and J. E. P., "An Efficient Modified Distributed Arithmetic Architecture Suitable for FIR Filter," 2021 Sixth International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Chennai, India, 2021, 89-93,
- M. M. Basha, P. S. R. Shashank, G. Rushikesh, K. V. Reddy, G. G. Kumar and S. Gundala, "Distributed Arithmetic Based FIR Filter: FPGA Implementation," 2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT), Kamand, India, 2024, 1-4,
- G. Charan Kumar and S. Shiyamala, "Efficient Architectures of FIR Filters using Distributed Arithmetic," 2024 3rd International Conference on Automation, Computing and Renewable Systems (ICACRS), Pudukkottai, India, 2024, 129-133,
- K. k. Bhadavath and Z. M. Livinsa, "An Efficient Approximation Look Up Table Based Distributed Arithmetic (DA) VLSI Architecture for Finite Impulse Response," 2022 2nd International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE), Greater Noida, India, 2022, 1849-1852.
- C. Chen, V. Romashchenko, M. Brutscheck and I. Chmielewski, "Performance Analysis and Optimization of Distributed Arithmetic-Based Convolutional Algorithms for FIR Filters on FPGA," 2023 34th Irish Signals and Systems Conference (ISSC), Dublin, Ireland, 2023, pp. 1-6.
- S. M. Cho, P. K. Meher, L. T. Nhat Trung, H. J. Cho and S. Y. Park, "Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis," in IEEE Access, vol. 9, 2021. 34722-34735.
- Serrano, Javier. "Introduction to FPGA design." (2008).