Industrial Quality Prediction System through Data Mining Algorithm
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Comparative Analysis an Early Fault Diagnosis Approaches in Rotating Machinery by Convolution Neural Network
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Nakagami-m Fading Detection with Eigen Value Spectrum Algorithms
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Abstractive Summarization System
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Design of Adaptive Estimator for Nonlinear control system in Noisy Domain
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Automated Nanopackaging using Cellulose Fibers Composition with Feasibility in SEM Environment
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Comparative Analysis of Temperature Measurement Methods based on Degree of Agreement
Volume-3 | Issue-3
Transistor Sizing using Hybrid Reinforcement Learning and Graph Convolution Neural Network Algorithm
Volume-3 | Issue-3
A Review on Meshing Techniques in Biomedicine
Volume-3 | Issue-4
EL DAPP - An Electricity Meter Tracking Decentralized Application
Volume-2 | Issue-1
SMART STREET SYSTEM WITH IOT BASED STREET LIGHT OPERATION AND PARKING APPLICATION
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ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET
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Abstractive Summarization System
Volume-3 | Issue-4
A Review on Meshing Techniques in Biomedicine
Volume-3 | Issue-4
MIMO BASED HIGH SPEED OPTICAL FIBER COMMUNICATION SYSTEM
Volume-1 | Issue-2
Industrial Quality Prediction System through Data Mining Algorithm
Volume-3 | Issue-2
Comparative Analysis of Temperature Measurement Methods based on Degree of Agreement
Volume-3 | Issue-3
Transistor Sizing using Hybrid Reinforcement Learning and Graph Convolution Neural Network Algorithm
Volume-3 | Issue-3
VIRTUAL REALITY SIMULATION AS THERAPY FOR POSTTRAUMATIC STRESS DISORDER (PTSD)
Volume-1 | Issue-1
Comparative Analysis an Early Fault Diagnosis Approaches in Rotating Machinery by Convolution Neural Network
Volume-3 | Issue-2
Volume - 3 | Issue - 3 | september 2021
Published
18 October, 2021
Transistor sizing is one the developing field in VLSI. Many researches have been conducted to achieve automatic transistor sizing which is a complex task due to its large design area and communication gap between different node and topology. In this paper, automatic transistor sizing is implemented using a combinational methods of Graph Convolutional Neural Network (GCN) and Reinforcement Learning (RL). In the graphical structure the transistor are represented as apexes and the wires are represented as boundaries. Reinforcement learning techniques acts a communication bridge between every node and topology of all circuit. This brings proper communication and understanding among the circuit design. Thus the Figure of Merit (FOM) is increased and the experimental results are compared with different topologies. It is proved that the circuit with prior knowledge about the system, performs well.
KeywordsTransistor Sizing Graph Convolutional Neural Network (GCN) Reinforcement Learning (RL) Figure of Merit (FOM) Nodes and Topology
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