Journal of Electronics and Informatics
IRO Journals
Volume 8 — Issue 1 — March 2026

High-Data-Retention 6T SRAM with Dual Sleep-Transistor Power-Gating and Duty-Cycle Aware Energy Analysis for Low-Power IoT Application

https://doi.org/10.36548/jei.2026.1.003
Varshitha K.
Department of Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha University, Chennai, India
Boya Sri Vyshnavi Valmiki
Department of Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha University, Chennai, India
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How to Cite

K., Varshitha, and Boya Sri Vyshnavi Valmiki. 2026. “High-Data-Retention 6T SRAM With Dual Sleep-Transistor Power-Gating and Duty-Cycle Aware Energy Analysis for Low-Power IoT Application”. Journal of Electronics and Informatics 8 (1): 52-67. https://doi.org/10.36548/jei.2026.1.003.
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Keywords

— Low-Power SRAM
— Dual Sleep Transistor
— Power Gating
— Data Retention
— Deep Sleep Mode
— IoT Applications
— Leakage Reduction
Published: 20-03-2026

Abstract

Static Random Access Memory (SRAM) is the main contributor to standby power dissipation in duty-cycled Internet of Things (IoT) systems. The paper presents a 6 transistor SRAM cell that has low leakage and dual sleep transistor-based power gating. The memory cell is mode aware and supports different modes of operation. The header PMOS and footer NMOS sleep transistors have been used to minimize leakage and retain stored information during extended periods of sleep. The proposed memory architecture is validated through 45 nm CMOS models and simulations in LT spice. The memory is able to achieve picoampere levels of supply current in deep sleep mode. A duty cycle aware analysis of energy dissipation is also presented. The analysis shows that the proposed memory is an effective solution for ultra-low-power memory in IoT systems.

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