IRO Journals
Journal of Electronics and Informatics

Design and Implementation of a SEC-DED-DAEC-STEC Error Control Code for Reliable Memory System

Open Access
Published: 25 June, 2026
Pages: 217-234
  • Rathinavel Pandian A. , Rathinavel Pandian A.
    Professor, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
    Professor, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
  • Rasvica Sweety M. , Rasvica Sweety M.
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
  • Nandhini S. , Nandhini S.
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
  • Negha C. , Negha C.
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
  • Sowmiya J. Sowmiya J.
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
    Student, Department of Electronics and Communication Engineering, V V College of Engineering, Thoothukudi, India
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How to Cite

A., Rathinavel Pandian, Rasvica Sweety M., Nandhini S., Negha C., and Sowmiya J. 2026. “Design and Implementation of a SEC-DED-DAEC-STEC Error Control Code for Reliable Memory System”. Journal of Electronics and Informatics 8 (3): 217-34. https://doi.org/10.36548/jei.2026.3.002.
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Keywords

Selected Triple-Bit Error Pattern Correction (STEC)
Triple Error Detection (TED)
Advanced Error Correction Codes (ECC)
Multi-Bit Upset Mitigation
Reliable SRAM Architecture
Syndrome-Based Error Localization
Fault-Tolerant VLSI Systems
Hardware Reliability Enhancement

Abstract

Modern memory systems are vulnerable to soft errors caused by radiation effects, electrical noise, and process variations, leading to single-bit and multi-bit upsets. The conventional error correction techniques like Hamming and SEC-DED codes have very few defenses against multi-bit complex fault models. In this paper, a (14,8) SEC-DED-DAEC-STEC code is proposed with capabilities of Single Error Correction (SEC), Double Error Detection (DED), Double Adjacent Errors Correction (DAEC) along with selective Triple Bit error pattern corrections. The proposed scheme uses six parity bits with syndrome lookup technique to correct the fault patterns. It is based on parity check matrix and syndrome based localization to increase the fault tolerance with moderate hardware cost. The Encoder/Decoder design has been developed using Verilog HDL and validated through Xilinx ISE environment. The experiment results prove successful correction of single bit, adjacent double bit and selective triple bit fault patterns whereas the uncorrectable faults are detected and flagged properly. The synthesis results of FPGA technology prove the maximum frequency and critical path delay as 182 MHz and 5.48 ns respectively.

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