Abstract
The fundamental operations of the communication are the multiplication and division. The multiplier usually consumes a larger area and power and poses a very high latency. As all the above mentioned characteristics of the multiplier depends on the techniques utilized for the multiplication. It becomes necessary to put into effect a proper multiplier that reduces both the latency and the power consumption. So the paper analysis the performance of the various multipliers and scopes to develop a low power high speed multiplier based on the Baugh Wooley algorithm. The Performance analysis of the Baugh Wooley multiplier and the other existing multipliers is done and was found that the performance of the Baugh Wooley in terms of the latency and the power consumption was convincing compared to the other existing methods.
References
- Rao, Pachara V., Cyril Prasanna Raj, and S. Ravi. "Vlsi design and analysis of multipliers for low power." In 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, pp. 1354-1357. IEEE, 2009.
- Khatibzadeh, Amir, and Kaamran Raahemifar. "A novel design of a 6-GHz 8/spl times/8-b pipelined multiplier." In Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), pp. 387-391. IEEE, 2005.
- Khatibzadeh, Amir Ali, Kaamran Raahemifar, and Majid Ahmadi. "A 1.8 V 1.1 GHz novel digital multiplier." In Canadian Conference on Electrical and Computer Engineering, 2005., pp. 686-689. IEEE, 2005.
- Prabhu, A. S., and V. Elakya. "Design of modified low power booth multiplier." In 2012 International Conference on Computing, Communication and Applications, pp. 1-6. IEEE, 2012.
- Kakde, Sandeep, Shahebaj Khan, Pravin Dakhole, and Shailendra Badwaik. "Design of area and power aware reduced Complexity Wallace Tree multiplier." In 2015 International Conference on Pervasive Computing (ICPC), pp. 1-6. IEEE, 2015.
- Gomes, Savio Victor, P. Sasipriya, and VS Kanchana Bhaaskaran. "A low power multiplier using a 24-transistor latch adder." Indian Journal of Science and Technology 8, no. 18 (2015): 1-5.
- Senthilpari, C., K. Diwakar, and Ajay Kumar Singh. "High speed and high throughput 8× 8 bit multiplier using a Shannon-based adder cell." In TENCON 2009-2009 IEEE Region 10 Conference, pp. 1-5. IEEE, 2009.
- Khan, Shahabaz, Sandeep Kakde, and Yogesh Suryawanshi. "Performance analysis of reduced complexity Wallace multiplier using energy efficient CMOS full adder." In 2013 International Conference on Renewable Energy and Sustainable Energy (ICRESE), pp. 243-247. IEEE, 2013.
- Keerthana, L., and M. Nisha Angeline. "VLSI Design and FPGA Implementation of N Binary Multiplier Using N-1 Binary Multipliers."
- Bibi, Safia, Muhammad Obaid Ullah, and Muhammad Ali Shami. "Design and analysis of hybrid tree multipliers for reduction of partial products." Mehran University Research Journal of Engineering and Technology 37, no. 3 (2018): 483-492.
- Kumar, KS Ganesh, J. Deva Prasannam, and M. Anitha Christy. "Analysis of low power, area and high speed multipliers for DSP applications." International Journal of Emerging Technology and Advanced Engineering 4, no. 3 (2014).
- Fritz, Christopher, and Adly T. Fam. "Interlaced Partition Multiplier." IEEE Transactions on Computers 65, no. 8 (2015): 2672-2677.
- Verma, Shekhar, Dhirendra Kumar, and Gaganpreet Kaur Marwah. "New high performance 1-bit full adder using domino logic." In 2014 International Conference on Computational Intelligence and Communication Networks, pp. 961-965. IEEE, 2014.
- Halder, Mousam. "Implementation of high speed low power carry look ahead adder using Domino logic." International Journal of Applied Sciences and Engineering Research 1, no. 3 (2012): 446-451.
- Warrier, Rakesh, Chan Hua Vun, and Wei Zhang. "A low-power pipelined MAC architecture using Baugh-Wooley based multiplier." In 2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE), pp. 505-506. IEEE, 2014.
