Journal of Electronics and Informatics
IRO Journals
Volume 3 — Issue 2 — June 2021

A Taxonomical Review of Multiplexer Designs for Electronic Circuits & Devices

https://doi.org/10.36548/jei.2021.2.001
Malti Bansal
Department of Electronics & Communication Engineering, Delhi Technological University (DTU), Delhi
Harmandeep Singh
Department of Information Technology, Delhi Technological University (DTU), Delhi
Gaurav Sharma
Department of Information Technology, Delhi Technological University (DTU), Delhi
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How to Cite

Bansal, Malti, Harmandeep Singh, and Gaurav Sharma. 2021. “A Taxonomical Review of Multiplexer Designs for Electronic Circuits & Devices”. Journal of Electronics and Informatics 3 (2): 77-88. https://doi.org/10.36548/jei.2021.2.001.
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Keywords

— Multiplexers
— demultiplexers
— study
— comparison
Published: 23-04-2021

Abstract

This research paper reviews and briefly discusses about the multiplexers and demultiplexers. This research paper aims to explore the history of multiplexers, types of multiplexers, applications and the real-time use cases of multiplexers. Furthermore, it also includes a brief introduction on the different multiplexing techniques employed in analog and digital electronics, ongoing research studies and future research scope for multiplexers.

References

  1. Dalal, Ankit and Ankur Atri. “A General Overview of Multiplexer and Demultiplexer.” International Journal of Research 1 (2014): 1293-1298.
  2. Dean, Tamara (2010). Network+ Guide to Networks. Delmar. pp. 82– 85.
  3. Debashis, De (2010). Basic Electronics. Dorling Kindersley. p. 557. ISBN 9788131710685.
  4. Butzer, P. L., Dodson, M. M., Ferreira, P. J. S. G., Higgins, J. R., Lange, O., Seidler, P. and Stens, R. L.(2011) 'Multiplex signal transmission and the development of sampling techniques: the work of Herbert Raabe in contrast to that of Claude Shannon', Applicable Analysis, 90: 3, 643 — 688
  5. Bates, Regis J; Bates, Marcus (2007), Voice and Data Communications, ISBN 9780072257328
  6. Lipták, Béla (2002). Instrument engineers' handbook: Process software and digital networks.CRC Press. p. 343.
  7. Admin. (2021, January 5). What are Multiplexer and Types of Multiplexing Techniques? WatElectronics.com. https://www.watelectronics.com/what-is-multiplexer-and-types/
  8. Admin. Types of Multiplexers. ThomasNet. https://www.thomasnet.com/articles/automation-electronics/multiplexer-types/
  9. Admin. Multiplexer Design and Performance. ThomasNet. https://www.thomasnet.com/articles/automation-electronics/multiplexer-design/
  10. Rahmat Talib and Mohammad Faiz Liew Abdullah. (2017) "The Future Electrical Multiplexing Technique for High-Speed Optical Fibre", DOI: 10.5772/intechopen.68407.
  11. https://www.intechopen.com/books/optical-fiber-and-wireless-communications/the-future-electrical-multiplexing-technique-for-high-speed-optical-fibre.
  12. M. Bansal and J. Singh, "Qualitative Analysis of CMOS Logic Full Adder and GDI Logic Full Adder using 18 nm FinFET Technology," 2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE), Noida, India, 2019, pp. 404-407, doi: 10.1109/RDCAPE47089.2019.8979087.
  13. N. Raghav and M. Bansal, "Analysis of Power Efficient 6-T SRAM Cell with Performance Measurements," 2017 International Conference on Innovations in Control, Communication and Information Systems (ICICCI), Greater Noida, India, 2017, pp. 1-4, doi: 10.1109/ICICCIS.2017.8660819.
  14. M. Rawat, M. Bansal, “ Voltage Mode Two-Phase and Four-Phase Sinusoidal Oscillator using VDCC”, International Journal of Advanced Research in Electronics and Communication Engineering, 2015, Vol. 4, Issue 6, pp. 1687-1691.
  15. D. Ruhela, M. Bansal, “Adiabatic Vedic Multipler Design Using Chinese Abacus Approach”, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 4, Issue 4, pp. 81-85, 2015.
  16. M. Bansal, D. Ruhela, “High Speed and Area Efficient Vedic Multiplier using Adiabatic Logic”, Journal of Basic and Applied Engineering Research, Vol. 1, Issue 11, pp. 14-17, 2014.
  17. N. Raghav, M. Bansal, “Analytical Study of Full Adder Circuit using Modified Glitch Free Cascadable Adiabatic Logic”, International Conference on Advanced Production and Industrial Engineering (ICAPIE-2017), 2017.
  18. M. Bansal and J. Singh, "Qualitative Analysis of 2-bit CMOS Magnitude Comparator and GDI Magnitude Comparator using FinFET Technology (18nm)," 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, 2020, pp. 1323-1327, doi: 10.1109/ICOSEC49089.2020.9215251.
  19. M. Bansal and J. Singh, "Comparative Analysis of 4-bit CMOS Vedic Multiplier and GDI Vedic Multiplier using 18nm FinFET Technology," 2020 International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, 2020, pp. 1328-1332, doi: 10.1109/ICOSEC49089.2020.9215317.
  20. M. Bansal, H. Saxena, “Power-Delay Behaviour of Digital Circuits Designed using MOSFET, CNTFET and FinFET, with the Scope of Miniaturization in these Transistors”, International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), Vol. 9, Issue 2, pp. 64- 71 , 2020.
  21. M. Bansal, H. Saxena, “Comparative Analysis and Behavior of Digital Applications simulated using MOSFET, CNTFET and FinFET Transistors in HSPICE”, International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), Vol. 9, Issue 2, pp. 54-58, 2020.
  22. M. Bansal, H. Saxena, “High Speed and Low Power Consumption Multipliers using FinFET Technology”, International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), Vol. 9, Issue 2, pp. 59-63, 2020.
  23. M. Bansal, J. Singh, “CMOS MOSFET, FinFET and CNTFET: Qualitative Analysis”, National Conference on Emerging Trends in Electronics & Communication-2019, pp. 79-84, 2019.
  24. N. Raghav and M. Bansal, "Analytical study of high performance flip-flop circuits based on performance measurements," 2017 International Conference on Computing, Communication and Automation (ICCCA), Greater Noida, India, 2017, pp. 1543-1548, doi: 10.1109/CCAA.2017.8230047.
  25. D. Ruhela, M. Bansal, “Vedic Multiplier with Chinese Abacus Adder Design using Reversible Logic Gates”, 2nd International Conference on VLSI, Communication and Networks (VCAN-2015), pp. 9-12, 2015.
  26. M. Rawat, M. Bansal, “A Voltage mode biquad with lowpass, bandpass and notch outputs using Voltage Differencing Current Conveyor”, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 4, Issue 5, pp. 506-508, 2015.
  27. M. Bansal, D. Ruhela, “High Speed, Energy Efficient Vedic Multiplier using Adiabatic Logic Gates”, International Conference on Advances in Electrical, Power Control, Electronics & Communication Engineering (AEPCECE-2014), 2014.