Abstract
In order to meet all the expectations of consumers, today's technology is all equipped with large capacity memories. Additional factors include power consumption and delay, all of which are crucial in determining how well a gadget performs. Memory is an important factor of many widgets, and as devices get smaller, their size likewise gets less. Every computerized device, as a result, uses little power, and speed is of utmost importance. Since 6T Static Random Access Memory (SRAM) cells have advantages over other cells, the current scenario suggests that they are frequently employed for SRAM-based memory systems. Today's electronics businesses are primarily concerned with minimizing power consumption, with static and dynamic power dissipation being the two key considerations. Meeting customer demands, high bandwidth, low power, and fast-consuming storages are also required. The major objective of this research is to decrease the power dissipation of the SRAM. The main problem faced by the digital industry is the decrease of power and delay. By connecting two Complementary MOSFET inverters back-to-back, an SRAM cell can be set up in an easy and beneficial manner. This setup offers good noise immunity.
References
- Rabaey, J. M. and Pedram, M. 1996 Eds., Low Power Design Methodologies. Norwell, MA: Kluwer.
- K. Zhang et al., "A SRAM Design on 65nm CMOS Technology with Integrated Leakage Reduction," Symp.VLSI Circuits, pp. 294-295, June, 2004.
- S. Jim Hawkinson, Analysis and Performance comparison of CMOS and FinFET for VLSI applications, Muthayammal Engineering College, Rasipuram, Tamil Nādu, India, 2013. Analysis, University Teknologi Malaysia (UTM), 81310 Skudai, Johor, Malaysia, 2014.
- Ijjada S.R., Kumar S.V.S, Reddy M.D., Rahaman S.A., and Rao V.M. 2011 Design of low power and high-speed inverter, International Journal of Distributed and Parallel Systems (IJDPS), 2(5), pp.127- 135.
- K. Kanda et al., "Two Orders of Magnitude Leakage Power Reduction of Low Voltage SRAMs by Row-by-Row Dynamic Vdd Control (RRDV) Scheme ", EEE Int. ASIC/SOC Conf., Sept. 2002, vol, no., pp: 381-385.
- 14nm and Tam CMOS technologies to implement the 6T SRAM and observe the power and delay in the 6T SRAM cell. FINFET'S and CNT FET's can also be used in future for the implementation of the 6T SR.
- Lourts Deepak, Likhitha Dhulipalla, Performance Comparison of CMOS and FinFET based SRAM for 22nm technology, M S Ramaiah School of Advanced Studies, Bangalore, India, 2013.
- K. Mistry, et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging." IEDM Technical Digest, 2007, pp. 247–250.
- Jigyasa Panchal, Dr. Vishal Ramola, Design and Implementation of 6T SRAM using FinFET with LOW POWER application, Uttarakhand Technical University, Dehradun, India, 2017.
- Wei Lim, Cheng Siong Lim, Michael Loong Peng Tan, Huei Chaeng Chin, Performance Evolution of 14nm FinFET Based 6T SRAM cell functionality for DC and Transient circuit.
- K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang,B. Zheng, M. Bohr A 3-GHz 70Mb SRAM in 65nm CMOS ISSCC 2005 /SESSION 26 / NON- VOLATILE MEMORY / 26.1 Intel, Hillsboro.
- M. Yamaoka, et al., "0.4V Logic-Library-Friendly SRAM Array Using Rectangular- Diffusion Cell and Delta-Boosted-Array Voltage Scheme, "IEEE J. Solid-State Circuits, Vol. 39, No. 6, pp. 934-940, June, used in the future for the implementation of the 6T SRAM cell.