Abstract
In this paper, the 4x4 array multiplier was designed and its power Delay Product (PDP) was analyzed. An array of full adders and half adders is used in an array multiplier, a combinational circuit, to multiply two binary values. The total power consumed by the array multiplier can be minimized by introducing a hybrid adder which constitutes 20T. In the 20T hybrid adder maximum power consumption is mostly dependent on the performance of the 10T XOR-XNOR circuit. As a result, it offers both full swing output and good capabilities without the need for an external inverter. Therefore, the array multiplier was designed by a hybrid adder instead of a conventional adder circuit to achieve low power and delay efficient multiplier circuit. The hybrid adder circuit outperforms its counterparts showing that PDP reduces 18% more than available conventional full adders. Using 90nm CMOS technology, the suggested circuits' performance is evaluated by stimulating them in a cadence virtuoso environment.
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