Journal of Electronics and Informatics
IRO Journals
Volume 7 — Issue 2 — June 2025

FPGA Based 32-Bit Hybrid Ripple Ling Carry Adder

https://doi.org/10.36548/jei.2025.2.008
Neenu Joseph
Associate Professor, Dept. of ECE, Albertian Institute of Science and Technology, Kerala
Ashker Assis
Dept. of ECE, Albertian Institute of Science and Technology, Kerala
Arjun Bibin
Dept. of ECE, Albertian Institute of Science and Technology, Kerala
Aromal A.
Dept. of ECE, Albertian Institute of Science and Technology, Kerala
Thanzeel A R.
Dept. of ECE, Albertian Institute of Science and Technology, Kerala
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How to Cite

Joseph, Neenu, Ashker Assis, Arjun Bibin, Aromal A., and Thanzeel A R. 2025. “FPGA Based 32-Bit Hybrid Ripple Ling Carry Adder”. Journal of Electronics and Informatics 7 (2): 177-90. https://doi.org/10.36548/jei.2025.2.008.
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Keywords

— Ripple-Ling hybrid carry adder
— Ripple-carry adder (RCA)
— Carry-lookahead adder
— Ling-based parallel prefix adder
— Carry propagation
— Critical Path
Published: 01-07-2025

Abstract

The 32-bit Hybrid Ripple Ling carry adder uses a Ling-based parallel prefix adder for the upper 16 bits and a ripple-carry adder (RCA) for the lower 16 bits to optimize performance, power, and area efficiency for VLSI designs. While the Ling adder speeds up carry propagation for larger bits, the RCA minimizes area and power for smaller bit-widths. This hybrid structure offers high-speed, low-power operation while saving 12% power, 30%–40% area, and a worst-case delay of 0.182 ns in a 28 nm process. The adder employs a Ling-based parallel prefix topology for the higher-order bits. A re-expression of the carry-lookahead technique is used to construct ling adders, which reduce the complexity of the carry-propagation process and allow for a higher speed carry calculation. The Ling adder's parallel prefix character suggests that multiple bits' carry signals are computed in parallel, significantly reducing the total delay. For the higher-order bits, where the carry chain length would normally be the dominant critical path, this speedup is especially important. The hybrid adder increases the global speed of the addition operation by reducing the critical path by using a Ling adder for the upper bits. The Xilinx Zynq-7000 SoC is used for the implementation.

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