Journal of Electronics and Informatics
IRO Journals
Volume 7 — Issue 3 — September 2025

Performance Analysis of High-Speed Parallel Prefix Adders for Arithmetic Applications

https://doi.org/10.36548/jei.2025.3.001
Banumathi J.
Research Scholar, ECE, School of Engineering and Technology, Dhanalakshmi Srinivasan University, Trichy
Karthy G.
Associate Professor, ECE, School of Engineering and Technology, Dhanalakshmi Srinivasan University, Trichy
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How to Cite

J., Banumathi, and Karthy G. 2025. “Performance Analysis of High-Speed Parallel Prefix Adders for Arithmetic Applications”. Journal of Electronics and Informatics 7 (3): 191-205. https://doi.org/10.36548/jei.2025.3.001.
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Keywords

— Digital Signal Processors (DSP). Parallel Prefix Adders (PPAs)
— Xilinx Vivado. Virtex FPGA
Published: 29-07-2025

Abstract

Research on affordable adder architectures has been spurred by the need for high-performance arithmetic in digital and embedded signal processors. Carry propagation affects speed, area, and power consumption by limiting two-operand addition, a fundamental operation in these systems. Because of their versatility in modifying particular performance metrics, Parallel Prefix Adders (PPAs) represent a viable substitute. The performance of various PPAs, including Kogge-Stone, Sparse Kogge-Stone, Spanning Tree, Brent-Kung, Han-Carlson, and Ladner-Fischer, on a Virtex-7 FPGA with Xilinx Vivado 2022.2 is investigated in this paper. The findings imply that each PPA design performs well in its own way and that no single design can offer the best balance of power, latency, and area. By taking performance parameter trade-offs into account, the research helps designers choose the best PPA for their design needs.

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