KUMAR, Veena Sanath; V., Karthik; N., Navashashank M; G., Puneeth; S, Sagar H. Design and Implementation of High Speed 6 – bit Current Steering DAC Modelling using Cadence. Journal of Electronics and Informatics, [S. l.], v. 6, n. 4, p. 332–341, 2025. DOI: 10.36548/jei.2024.4.004. Disponível em: https://irojournals.com/iroei/article/view/567. Acesso em: 21 mar. 2026.