A. RP, M. RS, S. N, C. N, J. S. Design and Implementation of a SEC-DED-DAEC-STEC Error Control Code for Reliable Memory System. J. Electron. Inform. [Internet]. 2026 Jun. 25 [cited 2026 Nov. 1];8(3):217-34. Available from: https://irojournals.com/iroei/article/view/2291