1.
Kumar VS, V. K, N. NM, G. P, S SH. Design and Implementation of High Speed 6 – bit Current Steering DAC Modelling using Cadence. JEI [Internet]. 2025 Feb. 8 [cited 2026 Mar. 21];6(4):332-41. Available from: https://irojournals.com/iroei/article/view/567