A Review on Low Power VLSI Design Models in Various Circuits
Abstract
Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.
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Madhura, S.. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (2022): 74-81. doi: 10.36548/jei.2022.2.002
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Madhura, S. (2022). A Review on Low Power VLSI Design Models in Various Circuits. Journal of Electronics and Informatics, 4(2), 74-81. https://doi.org/10.36548/jei.2022.2.002
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Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics, vol. 4, no. 2, 2022, pp. 74-81. DOI: 10.36548/jei.2022.2.002.
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Madhura S. A Review on Low Power VLSI Design Models in Various Circuits. Journal of Electronics and Informatics. 2022;4(2):74-81. doi: 10.36548/jei.2022.2.002
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S. Madhura, "A Review on Low Power VLSI Design Models in Various Circuits," Journal of Electronics and Informatics, vol. 4, no. 2, pp. 74-81, Jun. 2022, doi: 10.36548/jei.2022.2.002.
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Madhura, S. (2022) 'A Review on Low Power VLSI Design Models in Various Circuits', Journal of Electronics and Informatics, vol. 4, no. 2, pp. 74-81. Available at: https://doi.org/10.36548/jei.2022.2.002.
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@article{madhura2022,
author = {S. Madhura},
title = {{A Review on Low Power VLSI Design Models in Various Circuits}},
journal = {Journal of Electronics and Informatics},
volume = {4},
number = {2},
pages = {74-81},
year = {2022},
publisher = {IRO Journals},
doi = {10.36548/jei.2022.2.002},
url = {https://doi.org/10.36548/jei.2022.2.002}
}
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Keywords
CMOS
leakage power
transistor reduction
logic gates
low-power circuits
