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Home / Archives / Volume-5 / Issue-2 / Article-1

Volume - 5 | Issue - 2 | june 2023

The Power Optimization and an Area Efficient of Static RAM 1-Bit Cell using CMOS Novel Technologies
Gaje Sahruday  , Anumula Srikanth, Karne Harikrishna
Pages: 104-123
Cite this article
Sahruday, G., Srikanth, A. & Harikrishna, K. (2023). The Power Optimization and an Area Efficient of Static RAM 1-Bit Cell using CMOS Novel Technologies. Journal of Electronics and Informatics, 5(2), 104-123. doi:10.36548/jei.2023.2.001
Published
23 May, 2023
Abstract

In order to meet all the expectations of consumers, today's technology is all equipped with large capacity memories. Additional factors include power consumption and delay, all of which are crucial in determining how well a gadget performs. Memory is an important factor of many widgets, and as devices get smaller, their size likewise gets less. Every computerized device, as a result, uses little power, and speed is of utmost importance. Since 6T Static Random Access Memory (SRAM) cells have advantages over other cells, the current scenario suggests that they are frequently employed for SRAM-based memory systems. Today's electronics businesses are primarily concerned with minimizing power consumption, with static and dynamic power dissipation being the two key considerations. Meeting customer demands, high bandwidth, low power, and fast-consuming storages are also required. The major objective of this research is to decrease the power dissipation of the SRAM. The main problem faced by the digital industry is the decrease of power and delay. By connecting two Complementary MOSFET inverters back-to-back, an SRAM cell can be set up in an easy and beneficial manner. This setup offers good noise immunity.

Keywords

Static Random Access Memory (SRAM) Low Power Consumption and Delay

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